Semiconductor integrated circuits are prone to electrostatic breakdown by static electricity charged on the human body or other similar sources. Such electrostatic discharge (ESD) causes breakdown of the PN junction surface and breakdown of various films and layers formed on the device such as oxide films.
Various techniques have been devised for protecting circuits against damage caused by electrostatic discharge, such as those generated from the human body. These circuits have become very important because the slightest handling by an individual during semiconductor processing or in a final product could create enough electrostatic discharge to break down an oxide film or PN junction, thus ruining the semiconductor device.
Some ESD protection devices and circuits use a combination of diodes and resistors to protect the semiconductor circuits. Other ESD protection circuits use various types of transistors, such as disclosed in U.S. Pat. No. 4,989,057 to Lu, which discloses a floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage to serve as a clamp for electrostatic discharge voltages, minimizing thermal power dissipation within the semiconductor layer.
U.S. Pat. No. 5,623,387 to Li, et al., uses a split bipolar transistor with the transistor layout exhibiting very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents current hogging, causing an ESD failure. The transistor uses the snap-back effect to increase current carrying capacity. The transistor layout has metal contacts that are positioned away from regions of high energy dissipation. The use of high-diffusing phosphorous in various N-type doped regions prevents sharp changes in electron density.
Other circuits do not use as many contacts and doped regions, but make use of a transistor with the emitter and base shorted to show a bistable behavior having a high impedance in the avalanche breakdown region and a low impedance in the bipolar snap-back region.
In such transistor devices, it is desirable to increase the clamping efficiency (i.e., limiting the voltage at a point in a circuit) by limiting the maximum voltage developed at the collector terminal. It is also desirable to have the smallest snap-back voltage to increase the device failure threshold during electrostatic discharge conditions.
These two requirements are typically mutually exclusive because a low collector-to-base breakdown voltage requires a generally low base dopant level, while a low clamping voltage during snap-back operation requires a high current gain and a generally high base dopant level.